There is a continuous desire to reduce the silicon area of System-on-a-Chip (SoC) packages. In fact, small footprint designs are desired to be efficiently integrated into mobile phones. However, integrating analog and digital functions into a chip can cause spurious emissions (also known as “spurs”) into the different analog bandwidths on the chip. More precisely, it can result in the coupling of digital spurs into the analog bandwidths (namely, both transmitter and receiver) and can severely degrade the performance of the transmitter and/or receiver. The digital spurs are mainly linked to the digital clocks and their associated harmonics propagating throughout the silicon or package, or could be the result of indirect injection, for instance coming from analog front-ends (which again may be either transmit or receive front-ends).
Thus, integrating analog and digital functions into a chip may be associated with the implementation of mitigation techniques that limit the perturbation caused by the digital spurs on the analog bandwidths. Interference Mitigation Management (IMM) techniques, such as frequency evasion may be used for this purpose. IMM techniques may include shifting the digital spurs out of the bandwidths involved in analog operations such as radio transmission. In certain implementations of such techniques, a High Frequency (HF) Phase Locked Loop (PLL) may be used to generate a digital clock signal that is further sent to one or more frequency dividers, in order to produce respective clock signals with a lower frequency. In this case, frequency evasion may be performed by changing an integer divider ratio for each digital clock, namely the ratio of each frequency divider, so as to change the corresponding clock frequency.
Disadvantageously, some issues may arise from this kind of implementation, especially when several frequency bands are to be simultaneously cleared of digital spurs. This is the case, for instance, in wireless communication systems where transmit and receive transmissions may be performed concurrently.
First, complex processing may be used to adjust the divider ratio for each digital clock during ongoing communications. Secondly, using integer clock dividers allows a limited range of available frequencies to be used, since the granularity of the available digital clocks is limited to an integer number. In addition, reducing the divider granularity imposes the desire for, at the same time, the chip be designed for coping with high clock rates, which makes its implementation complex, time consuming, and therefore costly.
Due to these difficulties, new advancements in this are desirable.